1. Field of the Invention
This invention relates generally to Semiconductor Chips and, more particularly, to Programmable Write-Once, Read-Only Semiconductor Memory Arrays having improved current sourcing and sinking characteristics.
2. Description of the Prior Art
In the past, programmable read-only semiconductor memory arrays (known as PROMS) have been fabricated and sold as important parts of small or larger electronic systems. For example, PROMS have become very popular for use in digital systems such as computer systems, where it was desirable to have a Read-Only memory as part of the system's architecture. Read-Only memory arrays of the programmable type describe a particular class of Read-Only memory that is first selectively programmed or written into to provide a relatively frozen or fixed, customized, Read-Only memory. Read-Only memories are generally made by manufacturers with a fixed custom memory content. However, a problem would develop if a mistake is made, or change of pattern is needed which would require that the Read-Only memory array would have to be redone. This causes delay and a long turn around time. Programmable Read-Only Memory (PROM) eliminates the above problem by allowing the customer to program the memory content. The PROM design is a compromise because the memory array requires large voltage and current to "write" (or program) into a blank chip and the programming circuit often represents a significant portion of the entire memory chip thereby dissipating more power and consuming large chip area. One of the major problems in the programming circuitry is the loss of voltage and current in the programming conductive path thus causing inadequate programming in some portion of the chip. This problem is particularly severe when the memory array is large.
In order to provide chips with only a single layer of metalization, it is necessary to use diffused or implanted N+ or P+ regions as underpass conductors.
The resistance of narrow, long diffused or implanted N+ or P+ regions created severe voltage drop problems for memory cells connected to the end portions of these regions farthest from the driver elements used to apply voltages to these regions. Thus, the memory cells connected at the end of the N+ or P+ regions farthest from the driver elements did not receive the same signal level as the memory cells connected closer to the driver elements.
Another problem associated with prior art PROM devices was the need to provide relatively high voltages to current generating or sourcing devices connected to Word or Bit lines in order to generate enough current to reach the memory cells connected to end portions of the Word or Bit lines with a sufficient current level necessary to perform a writing operation therein. This often required the use of large devices on the chip as well as high power consumption.
Accordingly, a need existed to provide a PROM device or chip that would minimize voltage drop and improve current sourcing.